EDN

MIPS debuts new cores, instruction set

SAN JOSE, Calif. — MIPS Technologies Inc. is upgrading two of its cores and introducing a new instruction set architecture. The products aim to expand the company's relatively small presence in 32-bit ...
EDN

MIPS Licenses 32-bit Architecture to Fulcrum

Mountain View, Calif.-based MIPS Technologies Inc. has licensed its 32-bit instruction-set architecture (ISA) to privately held Fulcrum Microsystems Inc. for use in high-speed wire line communications ...
Design-Reuse

MIPS Technologies licenses 32-Bit architecture to Intrisity for development of 2-GHz processors

MOUNTAIN VIEW, Calif., April 22, 2002 -- MIPS Technologies, Inc. (Nasdaq: MIPS, MIPSB), a leading provider of industry-standard processor architectures and cores for digital consumer and business ...
Electronic Design

Embedded: IDE Includes Instruction-Set Simulator For MIPS 24K Family

The Multi IDE now supports the MIPS 32-bit 24K cores—including the 24Kc, 24Kc Pro, 24Kf, and 24Kf Pro—that operate up to 500 MHz. It also supports the company's C, C++, EC++, and Ada95 compilers. Its ...
Embedded

Imagination updates MIPS Aptiv cores, adds 32/64 bit Warrior

Imagination Technology has just updated its family of MIPS Aptiv processor cores and revealed more details on a next generation 32/64 bit MIP Series 5 MIPS CPUs, code-named Warrior. With the ...