Cadence Tensilica HiFi iQ DSP IP is the sixth generation of the company's HiFi DSP family found in countless SoCs with audio ...
A new technical paper titled “MultiVic: A Time-Predictable RISC-V Multi-Core Processor Optimized for Neural Network Inference” was published by researchers at FZI Research Center for Information ...
The RISC-V Summit North America, held on 22-23 October 2025 in Santa Clara, California, showcased the latest CPU cores featuring new vector processors, high-speed interfaces, and peripheral subsystems ...
Unlock the full InfoQ experience by logging in! Stay updated with your favorite authors and topics, engage with content, and download exclusive resources. In this episode, Thomas Betts chats with ...
Eindhoven, NL – Oct. 21, 2025 – Axelera AI, a provider of AI hardware acceleration technology, today announced Europa, an AI processor unit (AIPU) designed for multi-user generative AI and computer ...
OpenAI, Broadcom to deploy 10 gigawatts of custom AI chips Roll out to begin in second half of 2026 OpenAI's custom AI chip racks to use Broadcom networking gear Move follows OpenAI's chip deals with ...
The CBM experiment at FAIR (GSI, Germany) is among the most significant upcoming projects in heavy-ion physics. It is designed to investigate the properties of dense baryonic matter under extreme ...
A new technical paper titled “Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication” was published by researchers at TU Dresden and Centre for Tactile Internet with ...
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